• It requires two internal address and they are A =0 or A = 1.
• It can be either memory-mapped or I/O-mapped in the system. The interfacing of 8259 to 8085 is shown in the figure is I/O mapped in the system.
• The low order data bus lines D0-D7 are connected to D0-D7 of 8259.
• The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.
• The 8259 requires one chip select signal. Using a 3-to-8 decoder generates the chip-select signal for
• The address lines A4, A5 and A6 are used as input to decoder.
• The control signal IO/M (low) is used as logic high enables for the decoder and the address line A7 is used as logic low enables for a decoder.
• The I/O ad4ressès of 8259 are shown in table-8.5.