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Functional Block Diagram of 8086 Microprocesso

8086 Microprocessor | Functional Block Diagram of 8086 Microprocessor | Block Diagram of Intel 8086

Functional Block Diagram of 8086 Microprocessor

The 8086 is a 16-bit microprocessor. The term 16-bit implies that its arithmetic logic unit, its internal registers, and most of its instructions are intended to work with 16-bit binary data. The 8086 has a 16-bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time. The 8086 has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory locations. 

8086 CPU is divided into 2 independent functional parts to speed up the processing namely BIU (Bus interface unit) & EU (execution unit).

Fig: Functional Block Diagram of Intel 8086 microprocessor

BIU: It handles all transfers of data and addresses on the buses for the execution unit.

  • Sends out addresses
  • Fetches instructions from memory.
  • Read/write data from/to ports and memory i.e. handles all transfers of data and addresses on the busses 

EU (execution unit)

  • Tells BIU where to fetch instructions or data from
  • Decodes instructions
  • Executes instructions 

Execution Unit

Instruction Decoder & ALU:

Decoder in the EU translates instructions fetched from the memory into a series of actions that the EU carries out.16-bit ALU in the EU performs actions such as AND, OR, XOR, increment, decrement, etc. 

FLAG Register:

It is a 16-bit register. 9-bit are used as different flags, the remaining bits unused


Fig: 16-bit flag register

Out of 9 flags, 6 are conditional (status) flags and three are control flags 

Conditional flags: 

These are set or reset by the EU on the basis of the results of some arithmetic or logic operation. 8086 instructions check these flags to determine which of two alternative actions should be done in executing the instructions.

  • OF (Overflow flag): is set if there is an arithmetic overflow, i.e. the size of the result exceeds the capacity of the destination location.
  • SF (Sign flag): is set if the MSB of the result is 1
  • ZF (Zero flag): is set if the result is zero
  • AF (Auxiliary carry flag): is set if there is a carry from lower nibble to upper nibble or from lower byte to upper byte
  • PF (Parity flag): is set if the result has an even parity
  • CF (Carry flag): is set if there is carry from addition or borrow from subtraction 

Control flags:

They are set using certain instructions. They are used to control certain operations of the processor.

  • TF (Trap Flag): for single stepping through the program
  • IF (Interrupt flag): to allow or prohibit the interruption of a program
  • DF (Direction flag): Used with string instructions 

General Purpose Registers (GPRs):

  • 8 GPRs AH, AL (Accumulator), BH, BL, CH, CL, DH, and DL are used to store 8-bit data.
  • AL register is also called the accumulator
  • Used individually for the temporary storage of data
  • GPRs can be used together (as register pairs) to store 16-bit data words. Acceptable register pairs are: 

AH-AL pair AX register

BH-BL pair BX register (to store the 16-bit data as well as the base address of the memory location) 

CH-CL pair CX register (to store 16-bit data and can be used as a counter register for some instructions like a loop)

DH-DL pair DX register (to store 16-bit data and also used to hold the result of 16-bit data multiplication and division operation)

Pointer and Index registers: SP (Stack Pointer), BP (Base pointer), SI (Source Index), DI (Destination index)

Pointer Registers:

The two pointer registers, SP and BP are used to access data in the stack segment. The SP is used as offset from the current Stack Segment during the execution of instructions that involve the stack. SP is automatically updated. BP contains the offset address and is utilized in based addressing mode. Overall, these are used to hold the offset address of the stack address.

Index Registers:

EU also contains a 16-bit source index (SI) register and a 16-bit destination index (DI) register. These registers can be used for the temporary storage of data similar to general-purpose registers. However, they are specially to hold the 16-bit offset of the data word. SI and DI are used to hold the offset address of the data segment and extra segment memory respectively.

Bus Interface Unit


When EU is decoding or executing an instruction, bus will be free at that time. BIU pre-fetches up to 6-instructions bytes to be executed and places them in QUEUE. This improves the overall speed because in each time of execution of new instruction, instead of sending address of next instruction to be executed to the system memory and waiting from the memory to send back the instruction byte, EU just picks up the fetched instruction byte from the QUEUE.

The BIU stores these pre-fetched bytes in a first-in-first-out (FIFO) register set called a queue. Fetching the next instruction while the current instruction executes is called pipelining. 

Segment Registers:

The BIU contains a dedicated address, which is used to produce the 20 bit address. The bus control logic of the BIU generates all the bus control signals, such as the READ and WRITE signals, for memory and I/O. The BIU also has four 16 bit segments registers namely:

  • Code segment: holds the upper 16 bits of the starting addresses of the segment from which BIU is currently fetching instruction code bytes.
  • Stack segment: store addresses and data while the subprogram executes
  • Extra segment: stores the upper 16 bits of starting addresses of two memory segments that are used for data.
  • Data segment: stores the upper 16 bits of starting addresses of two memory segments that are used for data. 

Code Segment Register (CS) and Instruction Pointer (IP)

All program instructions located in memory are pointed using 16 bits of segment register CS and 16 bits offset contained in the 16-bit instruction pointer (IP). The BIU computes the 20-bit physical address internally using the logical address which is the contents of CS and IP. 16-bit contents of CS will be shifted 4 bits to the left and then adding the 16-bit contents of IP. Thus, all instructions of the program are relative contents of IP. Simply stated, CS contains the base or start of the current code segment, and IP contains the distance or offset from this address to the next instruction byte to be fetched.


Fig: Diagram showing the addition of IP to CS to produce the physical address
of code byte Stack Segment Register (SS) and Stack Pointer (SP)

A stack is a section of memory to stores addresses and data while a subprogram is in progress. The stack segment registers points to the current stack. The 20-bit physical stack address is calculated from the SS and SP. The programmer can also use Base Pointer (BP) instead of SP for addressing. In this case, the 20-bit physical address is calculated using SS and BP.

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